LC87F72C8A

No.6712-2/24

(3) Minimum Bus Cycle Time: 100 ns (10 MHz)

Note: The bus cycle time indicates ROM read time.

(4) Minimum Instruction Cycle Time: 300 ns (10MHz)

(5) Ports

- Input/output ports

Data direction programmable for each bit individually :

26 (P1n, P30-P35, P70-P73, P8n)

Data direction programmable in nibble units :

8 (P0n)

(When N-channel open drain output is selected, data can be input in bit units.)

- Input ports :

2 (XT1,XT2)

- LCD ports

Segment output :

48 (S00-S47)

Common output :

4 (COM0-COM3)

Bias terminals for LCD driver

3 (V1-V3)

Other functions

Input/output ports :

48(PAn,PBn,PCn,PDn,PEn,PFn)

Input ports :

7 (PLn)

- Oscillator pins :

2 (CF1,CF2)

- Reset pin :

1 (RES)

- Power supply :

6 (VSS1-3,VDD1-3)

(6) LCD controller

- Seven display modes are available (static, 1/2, 1/3, 1/4 duty

× 1/2, 1/3 bias)

- Segment output and common output can be switched to general purpose input/output ports.

(7) Small signal detection (MIC signals etc)

- Counts pulses with the level which is greater than a preset value

- 2 bit counter

(8) Timers

- Timer 0: 16 bit timer / counter with capture register

Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register

Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit

Counter with 8-bit capture register

Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register

Mode 3: 16 bit counter with 16 bit capture register

- Timer 1: PWM / 16 bit timer with toggle output function

Mode 0: 2 channel 8 bit timer (with toggle output)

Mode 1: 2 channel 8 bit PWM

Mode 2: 16 bit timer (with toggle output) Toggle output from lower 8 bits is also possible.

Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.

- Base Timer

1) The clock signal can be selected from any of the following :

Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0

2) Interrupts of five different time intervals are possible.