AD6679-500EBZ datasheet(9/82 Pages) AD

Nome de Peças	AD6679-500EBZ

Descrição Electrónicos	135 MHz BW IF Diversity Receiver

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Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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AD6679

Data Sheet

Rev. B | Page 8 of 81

Parameter

Temperature

Min

Typ

Max

Unit

LOGIC OUTPUT (SDIO)

Logic Compliance

Full

CMOS

Logic 1 Voltage (IOH = 800 µA)

Full

0.8 × SPIVDD

V

Logic 0 Voltage (IOL = 50 µA)

Full

0.2 × SPIVDD

V

LOGIC OUTPUTS (FD_A, FD_B)

Logic Compliance

Full

CMOS

Logic 1 Voltage

Full

0.8

SPIVDD

V

Logic 0 Voltage

Full

0

V

Input Resistance

Full

30

kΩ

DIGITAL OUTPUTS (D0± to D13±, A Dx/Dy± and B Dx/Dy±,

DATA0± to DATA7±, DCO±, OVR±, FCO±, and STATUS±)

Logic Compliance

Full

LVDS

ANSI Mode

Differential Output Voltage (VOD)

Full

230

350

430

mV

Output Offset Voltage (VOS)

Full

0.58

0.70

0.85

V

Reduced Swing Mode

Differential Output Voltage (VOD)

Full

120

200

235

mV

Output Offset Voltage (VOS)

Full

0.59

0.70

0.83

V

SWITCHING SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling

rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.

Table 4.

Parameter

Temperature

Min

Typ

Max

Unit

CLOCK

Clock Rate (at CLK+/CLK− Pins)

Full

0.3

4

GHz

Sample Rate

Maximum1

Full

500

MSPS

Minimum2

Full

250

MSPS

Clock Pulse Width

High

Full

1000

ps

Low

Full

1000

ps

LVDS DATA OUTPUT

Data Propagation Delay (tPD)3

Full

2.225

ns

DCO± Propagation Delay (tDCO)3

Full

2.2

ns

DCO± to Data Skew—Rising Edge Data (tSKEWR)3

Full

−150

−25

+100

ps

DCO± to Data Skew—Falling Edge Data (tSKEWF)3

Full

−150

−25

+100

ps

DCO± and Data Duty Cycle

Full

44

50

56

%

FCO± Propagation Delay (tFCO)4

Full

2.2

ns

DCO± to FCO± Skew (tFRAME)4

Full

−150

−25

+100

ps

DCO Output Frequency

Full

500

MHz

Output Date Rate

Full

1000

Mbps

LATENCY

Pipeline Latency

Full

33

Clock cycles

NSR Latency5

Full

8

Clock cycles

NSR HB Filter Latency5

Full

24

Clock cycles

VDR Latency5

Full

8

Clock cycles

HB1 Filter Latency5

Full

50

Clock cycles

HB1 + HB2 Filter Latency5

Full

101

Clock cycles

HB1 + HB2 + HB3 Filter Latency5

Full

217

Clock cycles

HB1 + HB2 + HB3 + HB4 Filter Latency5

Full

433

Clock cycles

Fast Detect Latency

Full

28

Clock cycles

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