Data Sheet

AD7190

Rev. C | Page 7 of 40

TIMING CHARACTERISTICS

otherwise noted.

Table 2.

Parameter

Unit

Conditions/Comments1, 2

100

ns min

SCLK high pulse width

100

ns min

SCLK low pulse width

READ OPERATION

0

ns min

CS falling edge to DOUT/RDY active time

60

ns max

80

ns max

t23

0

ns min

SCLK active edge to data valid delay4

60

ns max

80

ns max

t55, 6

10

ns min

Bus relinquish time after CS inactive edge

80

ns max

0

ns min

SCLK inactive edge to CS inactive edge

10

ns min

SCLK inactive edge to DOUT/RDY high

WRITE OPERATION

0

ns min

CS falling edge to SCLK active edge setup time4

30

ns min

Data valid to SCLK edge setup time

25

ns min

Data valid to SCLK edge hold time

0

ns min

CS rising edge to SCLK edge hold time

1

2

See Figure 3 and Figure 4.

3

4

The SCLK active edge is the falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY

is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the

digital word can be read only once.

CIRCUIT AND TIMING DIAGRAMS

1.6V

TO

OUTPUT

PIN

50pF

Figure 2. Load Circuit for Timing Characterization