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MT9P001 Folha de dados(PDF) 3 Page - ON Semiconductor |
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MT9P001 Folha de dados(HTML) 3 Page - ON Semiconductor |
3 / 33 page MT9P001 www.onsemi.com 3 Figure 2. Typical Configuration (Connection) DOUT [11:0] PIXCLK FV LV STROBE SADDR RESET_BAR STANDBY_BAR SCLK SDATA TRIGGER VDD_IO2,3 VDD2,3 1μF VAA2,3 OE To controller From controller Master clock EXTCLK Notes: 1. A resistor value of 1.5 kW is recommended, but may be greater for slower two-wire speed. 2. All power supplies should be adequately decoupled. 3. All DGND pins must be tied together, as must all AGND pins, all VDD_IO pins, and all VDD pins. 48 Figure 3. 48-Pin iLCC 10 x 10 Package Pinout Diagram (Top View) 1 2 3 4 5 6 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 34 33 32 31 FRAME_VALID LINE_VALID STROBE DGND VDD_ IO VDD SADDR STANDBY_BAR TRIGGER RESET_BAR OE NC DOUT8 DOUT7 DOUT6 VDD_IO DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 PIXCLK EXTCLK 48 47 46 45 17 18 |
Nº de peça semelhante - MT9P001_17 |
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Descrição semelhante - MT9P001_17 |
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