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MT9V024 Folha de dados(PDF) 30 Page - ON Semiconductor |
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MT9V024 Folha de dados(HTML) 30 Page - ON Semiconductor |
30 / 40 page MT9V024/D www.onsemi.com 30 LVDS Data Bus Timing The LVDS bus timing waveforms and timing specifications are shown in Table 12 and Figure 37. Figure 37. LVDS Timing Data Rise/Fall Time (10% − 90%) Data Setup Time Data Hold Time LVDS Data Output (SER_DATAOUT_N/P) LVDS Clock Output (Shift_CLKOUT_N/P) Clock Rise/Fall Time (10% − 90%) Clock Jitter Table 15. LVDS AC TIMING SPECIFICATIONS (VPWR = 3.3V ± 0.3V; TJ = –40_C to +105_C; output load = 100 W; frequency 27 MHz) Parameter Minimum Typical Maximum Unit LVDS clock rise time − 0.22 0.30 ns LVDS clock fall time − 0.22 0.30 ns LVDS data rise time − 0.28 0.30 ns LVDS data fall time − 0.28 0.30 ns LVDS data setup time 0.3 0.67 − ns LVDS data hold time 0.1 1.34 − ns LVDS clock jitter − 92 ps |
Nº de peça semelhante - MT9V024_17 |
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Descrição semelhante - MT9V024_17 |
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