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PYTHON480 Folha de dados(PDF) 17 Page - ON Semiconductor |
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PYTHON480 Folha de dados(HTML) 17 Page - ON Semiconductor |
17 / 69 page PYTHON 480 www.onsemi.com 17 Sensor States Low Power Standby In low power standby state, all power supplies are on, but internally every block is disabled. No internal clock is running (PLL / LVDS clock receiver is disabled). Only a subset of the SPI registers is active for read/write in order to be able to configure clock settings and leave the low power standby state. The only SPI registers that should be touched are the ones required for the ‘Enable Clock Management’ action described in Enable Clock Management − Part 1 on page 18 Standby (1) In standby state, the PLL/LVDS clock receiver is running, but the derived logic clock signal is not enabled. Standby (2) In standby state, the derived logic clock signal is running. All SPI registers are active, meaning that all SPI registers can be accessed for read or write operations. All other blocks are disabled. Idle In the idle state, all internal blocks are enabled, except the sequencer block. The sensor is ready to start grabbing images as soon as the sequencer block is enabled. Running In running state, the sensor is enabled and grabbing images. The sensor can be operated in global master/slave modes. User Actions: Power Up Functional Mode Sequences Power Up Sequence Figure 17 shows the power up sequence of the sensor. The figure indicates that the first supply to ramp−up is the vdd_18 supply, followed by vdd_33 and vdd_pix respectively. It is important to comply with the described sequence. Any other supply ramping sequence may lead to high current peaks and, as consequence, a failure of the sensor power up. The clock input should start running when all supplies are stabilized. When the clock frequency is stable, the reset_n signal can be de−asserted. After a wait period of 10 ms, the power up sequence is finished and the first SPI upload can be initiated. NOTE: The ‘clock input’ can be LVDS clock input (lvds_clock_inn/p) in case the PLL is bypassed. Figure 17. Power Up Sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us SPI Upload > 10us Enable Clock Management − Part 1 The ‘Enable Clock Management’ action configures the clock management blocks and activates the clock generation and distribution circuits in a pre−defined way. First, a set of clock settings must be uploaded through the SPI register. These settings are dependent on the desired operation mode of the sensor. Table 6 shows the SPI uploads to be executed to configure the sensor for LVDS 10−bit serial mode, with the PLL. Note that the SPI uploads to be executed to configure the sensor for other supported modes are available to customers under NDA at the ON Semiconductor Image Sensor Portal: https://www.onsemi.com/PowerSolutions/myon/erCispFol der.do In the serial modes, if the PLL is not used, the LVDS clock input must be running. It is important to follow the upload sequence listed in Table 6. Use of Phase Locked Loop If PLL is used, the PLL is started after the upload of the SPI registers. The PLL requires (dependent on the settings) some time to generate a stable output clock. A lock detect circuit detects if the clock is stable. When complete, this is flagged in a status register. NOTE: Since the PLL is not used in CMOS mode, the lock detect status must not be checked for the CMOS Mode sensor. |
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