REV. B

AD8380

–10–

SVGA System Operation

An SVGA system is characterized by the requirement of six

channels of panel drive for each displayed color. Such a system

would use a single AD8380 per color.

With E/

O and all address bits A[0:2] set high, channel loading

commences on the first rising edge of CLK following a valid

assertion of the Start Sequence (STSQ) input. The second stage

latches, and therefore the video outputs, are updated on the

first falling edge of the clock following a valid Transfer (XFR)

signal. (See Figure 5 for signal timing details.)

t

1

t

2

50

5

0

t

7

2.0V

0.8V

t

7

2.0V

0.8V

t

3

t

4

t

5

t

6

DB[0:9]

CLK

STSQ/CS

XFR

Figure 5. Sequenced SVGA Timing (A[0:2] = HIGH, E/

O =

HIGH, See Table I)

Table I. Sequenced SVGA Data Byte to Channel Assignment

Channel Number

Data Byte Number

E/

O = HIGH

VID0

0

R/

L = LOW

VID1

1

VID2

2

VID3

3

VID4

4

VID5

5

Load Sequence Switching (Right/Left Control)

To facilitate image mirroring, the order in which channels are

loaded can be easily switched. When the voltage on the right/left

control input (R/

L) is low, the internal sequencer will load data

starting with Channel 0 and counting up to Channel 5. When

this voltage is high, channel loading will be in reverse order, from

Channel 5 down to Channel 0.

XGA System Operation

In an XGA system, twelve column drivers (two AD8380s) are

required for each color (refer to Figure 6). An “even/odd”

system, in which one AD8380 drives even numbered columns

and another drives odd numbered columns, can be easily imple-

mented as detailed in Figures 7 and 8. A clock at one-half the

pixel rate is applied to the CLK input. Even bytes are loaded on

the rising edge of the clock, while odd bytes are loaded on the

falling edge. Identifying whether a chip is to load on rising or falling

edges is done by setting the proper level on the E/

O input.

STSQ_A

STSQ_B

XFR

E/

O_A

R/

L

INV

E/

O_B

CLKIN

STSQ/CS

XFR

E/O

R/L

INV

3

DVCC

6

A[0:2]

VIDEO

OUT

CLK

AD8380

DEVICE “A”

DB[0:9]

STSQ/CS

XFR

E/

O

R/

L

INV

6

VIDEO

OUT

CLK

AD8380

DEVICE “B”

DB[0:9]

3

DVCC

VIDEO

DB[0:9]

DCLK/2

10

1 COLOR OF ‘EVEN/ODD’ XGA

A[0:2]

PANEL

CONTROLLER

IMAGE

PROCESSOR

Figure 6. Even/Odd: Outputs of Devices A and B are

Configured as Even and Odd Data Channels and Loading

Sequence Is Defined by Status of E /

O and R /L Inputs

t

1

t

2

t

3

t

4

t

5

t

6

DB[0:9]

CLK

(EVEN

CHIP)

STSQ

(EVEN

CHIP)

XFR

A0:A2 = HIGH

0

10

0

11

9

10

11

t

1

t

2

t

3

t

4

CLK

(ODD

CHIP)

STSQ

(ODD

CHIP)

Figure 7. Sequenced Even/Odd XGA Timing, A[0:2] =

HIGH (See Table II)

Table II. Sequenced Even/Odd XGA Data Byte to

Channel Assignment

Data Byte Number

Channel Number

R/

L = LOW

R/

L = HIGH

E/

O = HIGH

VID0

0

10

VID1

2

8

VID2

4

6

VID3

6

4

VID4

8

2

VID5

10

0

E/

O = LOW

VID0

1

11

VID1

3

9

VID2

5

7

VID3

7

5

VID4

9

3

VID5

11

1