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MM58241 Folha de dados(PDF) 4 Page - National Semiconductor (TI) |
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MM58241 Folha de dados(HTML) 4 Page - National Semiconductor (TI) |
4 / 8 page Functional Description (Continued) Figure 4 demonstrates the critical timing requirements be- tween CLOCK and DATA IN for the MM58241 To clear (reset) the display driver at power on or any time the following flushing routine may be used With the enable signal high clock in 32 zeroes Drive the enable signal low and the display will be blank It is recommended to clear the driver at power on In Figure 5 the ENABLE signal acts as an envelope and only while this signal is at a logic ‘1’ does the circuit accept CLOCK input signals Data is transferred and shifted in the internal shift register on the rising clock edge ie ‘0’ – ‘1’ transition When the ENABLE signal goes low the contents of the shift registers are latched and the display will show new data During data transfer the display will show old data DATA OUT is also provided on the MM58241 being output on the falling edge At any time the display may be blanked under processor control using the BLANKING CONTROL input Figure 6 shows a schematic diagram of a microprocessor- based system where the MM58241 is used to provide the grid drive for a 32-digit5x7dot matrix vaccum fluorescent (VF) display The anode drive in this example is provided by another member of the high voltage display driver family namely the MM58248 which does not require an externally generated load signal TLF5600 – 3 FIGURE 3a Output Impedance Off TLF5600 – 4 FIGURE 3b Output Impedance On Timing Diagrams TLF5600 – 5 For the purposes of AC measurements VIH e 24V VIL e 08V FIGURE 4 Clock and Data Timings 4 |
Nº de peça semelhante - MM58241 |
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Descrição semelhante - MM58241 |
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